A graphics board is a printed-circuit board that typically includes at least one graphics processor and other electronic components that process and display graphics or other video data in a computer system. FIG. 1 is a block diagram of a conventional graphics board 100 that includes a graphics processor 105. Typically, one of the electronic components connected to the graphics processor 105 is a double-data-rate random-access memory (DDS RAM) chip 106. Both the graphics processor 105 and the DDR RAM 106 typically have high power requirements as compared to other electronic components. For example, the graphics processor 105 typically requires 5-15 amps (A) of power at 1.6 volts (V), and the DDR RAM 106 typically 5-10 A and 10-20 A at 1.25 V and 2.5 V, respectively. Because the processor 105 and DDR RAM 106 have such high power requirements, pulse-width-modulated (PWM) switching power supplies 110a, 110b, and 110c are typically provided for the graphics processor 105 and the DDR RAM 106. Typically, the PWM power supplies 110a, 110b, and 110c each include a separate PWM-controller chip, although, these controllers can be integrated into the graphics processor 105 and DDR RAM 106 chips, respectively.
Ideally, the operating frequencies of the PWM power supplies 110a, 110b, and 110c are the same. If, however, these frequencies are different, undesirable “beat” frequencies can result. A beat frequency is equal to the difference between the two frequencies. Unfortunately, the beat frequency can cause undesirable artifacts to appear in a video display.
One technique for reducing or eliminating the beat frequency is to have a master clock chip 115 that generates a master clock signal for all three PWM power supplies 110a, 110b, and 110c. The PWM controllers 120a, 120b, and 120c will typically divide down the frequency of the master clock signal to a desired PWM frequency. For example, a typical frequency for the PWM power supplies 110a, 110b, and 110c can range from 100 kilohertz to 1 megahertz, and the master clock frequency may be an order of magnitude above the PWM frequency. By providing the same master clock frequency to all the PWM controllers 120a, 120b, or 120c, ideally all of the PWM signals should have the same frequency thus eliminating any beat frequency.
But, providing a master clock signal can have several disadvantages. Because the PWM controllers 120a, 120b, and 120c have high-impedance clock inputs noise may cause jitter and other artifacts on the master clock signal. Furthermore, the master clock signal paths to the PWM controllers 120a, 120b and 120c may have different propagation delays. Such jitter, artifacts, and signal delays may cause the PWM signals generated by the PWM controllers 120a, 120b and 120c to have different frequencies. Again, having different frequencies may give rise to a beat frequency that may cause visual artifacts in the video display. Furthermore, the master clock chip which takes up space on the graphics board 100 and, thus, increases component count, overall cost, and manufacturing complexity.
Another technique for reducing or eliminating the beat frequency is, instead of using a master clock chip 115, for two of the PWM controllers 120b, and 120c, (slaves) of the graphics board 105 to lock onto the PWM signal of the other PWM controller 120a (master) using a phase-locked loop (PLL). The slave PLLs can each generate one or more slave-PWM output signals that are phase locked to the master-PWM signal, and, that have the same frequency as the master-PWM signal. One problem with using a slave PLL, however, is that because it typically operates at a relatively low bandwidth (e.g. 100 Hz to 100 kHz) the PLL typically requires relatively large passive filter components (typically a capacitor) to set the bandwidth. Such a component is typically too large to be integrated onto a PWM controller chip 120, and thus, must be located on the graphics board 100 external to the PWM controller chip 120. Unfortunately, such an external component occupies space on the graphics board 100 and, thus, often increases the component count, overall cost and manufacturing complexity of the graphics board 105. Furthermore, the external component requires that the PWM controller chip 120 have an additional coupling pin and thus, often increases the size, cost, and manufacturing complexity of the PWM controller chip 120.
One technique for eliminating the external filter component requirement is to provide the PLL with a variable-gain charge pump. Such a charge pump includes multiple, parallel-output-drive stages that can be selectively activated to increase or decrease the output current, and thus the gain, of the charge pump. By increasing or decreasing the charge pump gain, one can respectively increase or decrease the PLL bandwidth. A problem with this technique, however, is that the multiple drive stages occupy a significant area of the PWM controller chip 120 that includes the PLL.